Efficient Hardware Implementations for the DES Family

Network data is, currently, often encrypted at a low level. In addition, as it is widely supported, the majority of future networks will use low-layer (IP level) encryption. Moreover, current trends imply that future networks are likely to be dominated by mobile terminals, thus, the power consumption and electromagnetic emissions aspects of encryption devices will be critical. This paper presents several realizations of one of the most widely used encryption algorithm, the DES/TripleDES, both in software and in hardware. We present software implementations of the algorithm running on two of the state-of-the-art Intel IXP network processors and several hardware realizations based on a standard-cell library. The hardware platforms presented appear to be optimal. Moreover, by placing and routing those designs, we have also realized that the commercial ASIC synthesis tools cannot accurately predict the area and the performance of the placed & routed final netlist in such designs, since the ASIC implementations of the encrypted algorithms include a very large number of wires and a limited number of logic CMOS cells. Key-Words: Cryptography, 3DES, AES, Software Implementation, Hardware Implementation